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SMASH 4.1 (free, functional, evaluation kit )
SMASH allows virtually any type of (meaningful) connection between the different models it supports. Not only SMASH provides the greatest flexibility in terms of modeling variety, but also the simplest interconnections, and thus the best usability. Analog signals can connect analog primitives (MOS devices, resistors etc.), analog behavioral modules (ABCD) ports, Verilog ports, and VHDL ports. For Verilog signals conversions are automatically supplied to translate logic levels into voltages and impedances. A default model is provided, which can be overridden by user-defined models and/or global parameters defaults. The accuracy of the conversion process at the analog/digital boundary is not limited by the simulator. A default model is provided, which provides sufficient accuracy in most cases. If the user thinks he needs more accuracy, he can customize the interface (about 80 parameters are available to do this...). For VHDL signals, the meaningful connections with the analog world involve std_logic signals, and also real type signals. Connections between Verilog and VHDL signals is also seamless. Standard conversions are applied between std_logic signals and the Verilog logic model.
Connecting models from different sources is very easy and flexible. A top-level file controls the top-level of the hierarchy. It may contains SPICE code, together with Verilog code and/or VHDL code. References to external SPICE subcircuits, Verilog modules or VHDL entities are resolved through the library mechanism. External (external to the main netlist) files in SPICE, ABCD, Verilog or VHDL can be used and referenced with simple statements from the pattern file. The whole mechanism is very simple, and walking through the files (which is often necessary, whatever the schematic package you use), to understand a design is quite simple. There are no cryptic interconnection files everywhere. This is not the case in other so called mixed signal solutions, where the directories and the files are incredibly complex, and practically unusable for debugging purpose.
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